Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of electronic devices. For example, a memory cell, such as a static random-access memory (SRAM) memory cell, may include a number of transistors. Thus, the size and density of the memory cells are constrained by the transistor size and density. Accordingly, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority. However, the size and density of the memory cells is fundamentally constrained by the number of transistors used in the memory cell.
In lieu of transistor-based memory cells, a crossbar memory element utilizes two-terminal hysteretic resistive switching elements to provide higher memory density. However, the array of resistive elements produce parasitic conduction paths that impair the ability to accurately read the digital value stored by an individual resistive element, thereby limiting the usefulness of crossbar memory elements.